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IS62LV2568L IS62LV2568LL
IS62LV2568L IS62LV2568LL
256K x 8 LOW POWER and LOW V++ CMOS STATIC RAM
FEATURES
Access times of 55, 70, 100 ns Low active power: 126 mW (max, L, LL) Low standby power: 36 W (max, L) and 7.2 W (max, LL) CMOS standby Low data retention voltage: 1.5V (min.) Available in Low Power (-L) and Ultra-Low Power (-LL) Output Enable (OE) and two Chip Enable TTL compatible inputs and outputs Single 2.7V-3.6V power supply Available in the 32-pin 8x20mm TSOP-1, 32-pin 8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA
DESCRIPTION The 1+51 IS62LV2568L and IS62LV2568LL are low power
and low VCC, 262,144-bit words by 8 bits CMOS static RAMs. They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV2568L and IS62LV2568LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TFBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
2048 x 128 x 8 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1 CE2 OE WE
CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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IS62LV2568L IS62LV2568LL
PIN CONFIGURATIONS
32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1
A11 A9 A8 A13 WE CE2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
48-Pin 6*8mm TF-BGA
1 A B C D E F G H
A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9
2
A1 A2
3
CE2 WE NC
4
A3 A4 A5
5
A6 A7
6
A8 I/O0 I/O1 Vcc GND
NC OE A10 CE1 A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
PIN DESCRIPTIONS
A0-A17 CE1 CE2 OE WE I/O0-I/O7 NC Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Data Input/Output No Connection Power Ground
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C 40C to +85C VCC 2.7V - 3.6V 2.7V - 3.6V
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TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB, ISB ISB, ISB ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value 0.5 to Vcc + 0.5 0.3 to +4.0 40 to +85 65 to +150 0.7 Unit V V C C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = 1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.2 2.2 0.3 1 1 Max. 0.4 VCC + 0.3 0.4 1 1 Unit V V V V A A
GND VIN VCC GND VOUT VCC
Notes: 1. VIL = 2.0V for pulse width less than 10 ns.
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IS62LV2568L IS62LV2568LL
IS62LV2568L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. -55 Min. Max. 40 45 0.4 1.0 35 50 -70 Min. Max. 30 35 0.4 1.0 35 50 -100 Min. Max. 20 25 0.4 1.0 35 50 Unit mA mA
VCC = Max., Com. VIN = VIH or VIL, Ind. CE1 VIH or CE2 VIL, f = 0 VCC = Max., f = 0 Com. CE1 VCC 0.2V, Ind. CE2 0.2V, or VIN VCC 0.2V, VIN 0.2V
ISB
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV2568LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. -55 Min. Max. 40 45 0.4 1.0 10 15 -70 Min. Max. 30 35 0.4 1.0 10 15 -100 Min. Max. 20 25 0.4 1.0 10 15 Unit mA mA
VCC = Max., Com. VIN = VIH or VIL, Ind. CE1 VIH or CE2 VIL, f = 0 VCC = Max., f = 0 Com. CE VCC 0.2V, Ind. CE2 0.2V, or VIN VCC 0.2V, VIN 0.2V
ISB
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time Min. 55 10 5 10 10 0 -55 Max. 55 55 55 30 20 20 Min. 70 10 5 0 10 10 0 -70 Max. 70 70 70 35 25 25 -100 Min. Max. 100 15 5 0 10 10 0 100 100 100 50 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE1 tACE2 tDOE
tLZOE(2) OE to Low-Z Output tHZOE(2) OE to High-Z Output tLZCE1 tLZCE2
(2) (2)
CE1 to Low-Z Output CE2 to Low-Z Output
tHZCE(2) CE1 or CE2 to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.5V See Figures 1 and 2
AC TEST LOADS
1 TTL OUTPUT 100 pF Including jig and scope
OUTPUT 5 pF Including jig and scope 1 TTL
Figure 1
Figure 2
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IS62LV2568L IS62LV2568LL
AC TEST LOADS READ CYCLE NO.1(1,2)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
AC WAVEFORMS READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE1
tACE1/tACE2
tLZOE
CE2
tLZCE1/ tLZCE2
HIGH-Z
tHZCE
DATA VALID
DOUT
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIL. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time
(4)
Min. 55 45 45 45 0 0 50 25 0 5
-55
Max. 25
Min. 70 65 65 65 0 0 55 30 0 5
-70
Max. 25
-100 Min. Max 100 80 80 80 0 0 70 40 0 5 30
Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
(3) (3)
WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH.
AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2)
tWC
ADDRESS
tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE(4) tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
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IS62LV2568L IS62LV2568LL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
tWC
ADDRESS
tSA tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE(4)
WE
tHZWE tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the HIGH-z state if OE =VIH.
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DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vcc = 2.0V, CE1 Vcc 0.2V Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Min. 1.5 0 Max. 3.6 20 5 25 7 Unit V A A A A ns ns
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
tRC
DATA RETENTION WAVEFORM
tSDR VCC 2.7V
(CE1 Controlled)
Data Retention Mode tRDR
2.2V
VDR CE1 VCC - 0.2V
CE GND
DATA RETENTION WAVEFORM
(CE2 Controlled)
Data Retention Mode
VCC 2.7V
t SDR
CE2 2.2V VDR 0.4V GND CE2 0.2V
t RDR
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IS62LV2568L IS62LV2568LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 55 IS62LV2568L-55T IS62LV2568L-55H IS62LV2568L-55B IS62LV2568L-70T IS62LV2568L-70H IS62LV2568L-70B IS62LV2568L-100T IS62LV2568L-100H IS62LV2568L-100B Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 55 IS62LV2568L-55TI IS62LV2568L-55HI IS62LV2568L-55BI IS62LV2568L-70TI IS62LV2568L-70HI IS62LV2568L-70BI IS62LV2568L-100TI IS62LV2568L-100HI IS62LV2568L-100BI Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA
70
70
100
100
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000
Integrated Circuit Solution Inc.
BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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